1. Field of Invention
The present invention relates to the design and system of a test pattern source generator. More particularly, the present invention relates to the design and system of a test pattern source generator that uses hardware to perform software simulation.
2. Description of Related Art
By convention, a test pattern is used to test an integrated circuit (IC). By tapping the resulting signals in an alternating current (AC) signal analyzer, a failure analysis (FA) of the IC is carried out. Hence, the generator for producing the test pattern is an important tool associated with an AC signal analysis. In general, the test pattern system must be compact and compatible with most FA equipment such as an E-beam, EMMI or probe station. To increase positioning accuracy and success rate of a FA, early acquisition of signal input/output relationships of each standard cell inside the IC is important. The AC signal source for conducting an FA, whether a measurement of detection signal inside the IC or a contrasting analysis with an E-beam-like image, is often provided by a test pattern generator. The test pattern generator produces a series of repeat runs of a dynamic signal. During a loop testing, the AC signal is expected to be stable and continuous so that clock delay time is minimized as much as possible.
A conventional test pattern generator frequently uses software simulation to produce the required test pattern. By inputting software simulated test patterns into a test IC connected to an FA station, defects inside the test IC may be detected and accurately positioned. However, the test patterns produced by a conventional test pattern generator often lead to a few problematic conditions:    1. When an EMMI FA device is used to conduct the analysis, the test pattern may position errors inside the test IC using DC signals only. Ultimately, the detection is limited to DC failure analysis such as the positioning of hot spots.    2. When a logic analysis (LA) pattern generator and an E-beam FA device are used in tandem, image flashing may occur. Such occurrence is the result of a very short test pattern execution time (in microseconds) compared with a very long processing period (in seconds) of the software/hardware stages inside the LA pattern generator due to loop delay.    3. The same situation as the one described above appears in more advanced testing stations such as the SC model. The processing time for processing a 10 Mhz testing frequency loop back delay is about 2 μs.    4. When a PC module board and an E-beam are used in tandem and a simple test pattern signal is used to carry out an image analysis of an IC, program loop and loop back delay both affect the measurement of the test signals.
Hence, test patterns are often limited to DC signals due to a special relationship with an FA device or test patterns are measured with difficulties due to loop back delay of software generated test patterns.